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ke7c2mi

•Created by ke7c2mi on 9/9/2024 in #pcb-and-analog

Designing an SDR with PoE Power Supply: Synchronizing SMPS and Managing Heat and Noise

Hey all! Background at the start, I invite comments on it but core questions are at the bottom 🙂 Primarily an embedded sw eng who dabbles a bit in hardware from time to time. I've always wanted to make an SDR and have been hashing out a high level design for one - it boils down to some ECP5 FPGA based board, gigabit etherenet, a DRAM chip, all powered by PoE with some SDR payload. The SDR payload is still a little open, I will either use something integrated like AT86RF215 or use a mixer + ADC - one thing for certain is I will include a MAX2769 for messing about with GNSS signals to try and extract very accurate timing information (this is the core goal, based on some other SDR projects I played with in the past) Just now I have been looking at how to power the system. For PoE I found several reference designs with LM5070 and plan to use that for the main PSU.

Ethernet phy:
     3.3V (phy) ~100ma
     2.5V-3.3V (digital interface) ~50ma
     1.2V (Phy core) ~200ma

ECP5:
     2.5 Vaux ~100ma
     1.1 Vcore ~500ma
     ... various VCCIO voltages for banks
DRAM:
     1.35v-1.5v ~400ma

QSPI Flash:
     2.5v ~ 100ma

SDR:
     3.3v ~ 500ma?
     .... various VCCIO voltages for digital interface

Ethernet phy:
     3.3V (phy) ~100ma
     2.5V-3.3V (digital interface) ~50ma
     1.2V (Phy core) ~200ma

ECP5:
     2.5 Vaux ~100ma
     1.1 Vcore ~500ma
     ... various VCCIO voltages for banks
DRAM:
     1.35v-1.5v ~400ma

QSPI Flash:
     2.5v ~ 100ma

SDR:
     3.3v ~ 500ma?
     .... various VCCIO voltages for digital interface

Now normally as an SWE, the hardware I do make is test hardware or silly toys, there aren't many constraints and I get to be lazy and slap down a bunch of LDOs and not worry about it.....

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