Designing an SDR with PoE Power Supply: Synchronizing SMPS and Managing Heat and Noise
Hey all! Background at the start, I invite comments on it but core questions are at the bottom 🙂
Primarily an embedded sw eng who dabbles a bit in hardware from time to time. I've always wanted to make an SDR and have been hashing out a high level design for one - it boils down to some ECP5 FPGA based board, gigabit etherenet, a DRAM chip, all powered by PoE with some SDR payload. The SDR payload is still a little open, I will either use something integrated like AT86RF215 or use a mixer + ADC - one thing for certain is I will include a MAX2769 for messing about with GNSS signals to try and extract very accurate timing information (this is the core goal, based on some other SDR projects I played with in the past)
Just now I have been looking at how to power the system. For PoE I found several reference designs with LM5070 and plan to use that for the main PSU.
Now normally as an SWE, the hardware I do make is test hardware or silly toys, there aren't many constraints and I get to be lazy and slap down a bunch of LDOs and not worry about it.....
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In this design there are 2 conflicting concerns - heat dissipation and noise. Ideally, I could just use the LM5070, drop to 3.3v and LDO everything from there, then the system only has a single SMPS and there are no issues with them interacting. In practice I think this will lead to burning up too much power on the board and things getting hot (whilst we are only talking about a couple of watts here, it's in addition to the power that's actually used, I am currently aiming for the board to be 50mm x 150mm and I'd like to avoid needing an enclosure and heat pad to keep it under control)
So - I think I need LM5070 to drop PoE to some intermediate voltage, and then some multiple buck PMIC to drop to the actual voltages I care about.
As I understand it, when we have two free running buck converters we can get "wobbly harmonics" from their interaction, where if they were locked together then the harmonic pattern would be static - which would be preferrable for something which wants to measure RF signals.
I've found some suitable parts for this, but the one I like the most, TPS65217A (I would like DVS, happy to talk about this - the thought is that it will allow me to play with any noise I find on the board and tweak power consumption.. maybe I can try to overclock the ECP5 some day). The problem I found is that it doesn't have a clock input or output, so I could never synchronise it against the LM5070. It also doesn't have any way to tweak the oscillator speed - with the LM5070 there is a clock input that I could drive back from the FPGA after boot which would let me twiddle the frequency, in theory moving any harmonics.
TL;DR questions:
1: When to think about synchronising SMPS together? Am I overthinking the whole thing? Is it possible enough to have the LM5070 @ 600KHz and the TPS65217A @ 2.25Mhz and they are unrelated enough there is not a high chance of a problem?
2: Are there better strategies / perspectives to use in looking at this?
3: Is using a very integrated PMIC like TPS65217A in an application like this even a good idea? I picked it because it's highly integrated and make roughly the voltages I want, DVS and current sensing are "Nice to have" and it does it all. Are there other parts I should be looking at?
4: Is there a poor mans guide for simulating PDNs - could I investigate this better before making it? (I've tried to play with OpenEMS several times, I'm not against trying again, but it's a LOT of work). My knowledge of IBIS is mostly that it is a bird.
5: Anyone want to route a DDR3 interface some time in the future (or more general collaboration!)
6: What have I totally missed or not even though about here? (I accept I could be providing some tangible goal for noise, I do not have one today less is better)
(Pardon the wall of text.... I can share the project next time, after I tidy it up a bit 😛 )
@ke7c2mi @ShreeshaN @hemalchevli, maybe we can get some quid pro quo going 🤓
At the lower end of the spectrum I can somewhat get my head around mosfet properties, but when it gets critical I make myself scarce. 12V is a big voltage 😄
That said - I suspect that the other mosfets have more gate capacitance, or need more Vgs to fully switch on.
The extra gate capacitance is a cost of switching energy, it will heat up because you are charging and discharging a capacitor - it will always be there.
Heating from not turning off an on fast enough I thnk would be more load dependant.
@Afuevu can you show the relevant parameters for the mostfets you changed? Gate capacitance and Vgs threshold are I think what matters here. If the gate capacitance of the new mosfet is a lot higher that may do it.
Take anything I say RE electronics with a pinch of salt, backseat HWeng at best
If you don't want to spend time designing PoE, there are some modules available from silvertel, I'm sure you will find one that fits your power budget.
There is poor man PDN for layout but it takes a lot of time to setup. I used ElmerFEM and bunch of other softwares to get there.
Thanks for the suggestion! I had a thought to use a module - I originally built some years a similar system where I used a RPI with a PoE board and generally built it from modules.
That design uses more power, has way more computer than I need at the SDR.etc and it is quite noisy too which you can see with the SDR - here I am hoping to crunch down to something that can easily be put in an enclosure outside and pole mounted so using modules is less appealing due to the size.
I do plan to use a magjack with all the integrated magnetics to save some amount of faf, but at the end of the day I wanted to include a DDR3L chip so the PoE is the least of my problems compared to trying to tame that kthulu beast 🤓
Imagine some aluminum extruded box mounted to a pole, aiming for 50mmx150mm - with an ethernet cable in the bottom and a couple of SMA connectors on top running to antennas
I have done routing for high speed interface like USB3.2, PCIe etc.
Routing single DDR chip should be doable, there are some challenges with routing more chips.
@ke7c2mi What CAD you are using/planning to use for this design?
Kicad 🤓
I'm still messing about with the schematic just now so I'm not routing properly yet, I did have one try at fanning out the DDR3 just to see how bad it was and it was in the "not impossible" category for me!
I'll ping you when I have something toshare