Sterling
DIIDevHeads IoT Integration Server
•Created by Sterling on 7/25/2024 in #firmware-and-baremetal
How can I create and implement DDR memory in Verilog on an FPGA?
Well, you will have to measure the total bandwidth utilization of the DDR controller, find out if it could achieve around 76-83% of the theoretical maximum bandwidth.
If this isn't enough to meet your 512MB/s per port requirement, you can as well to use the on-chip memory in to the support to the DDR controller, it will help you to meet your bandwidth requirements, and you will observe that this could reduce latency compared to using just the DDR controller.
7 replies
DIIDevHeads IoT Integration Server
•Created by Sterling on 7/25/2024 in #firmware-and-baremetal
How can I create and implement DDR memory in Verilog on an FPGA?
Ohh...Ok thanks 👍 @Sterling
But ,do u have any idea on how to evaluate the performance of the DDR controllers in terms of latency and bandwidth?
7 replies
DIIDevHeads IoT Integration Server
•Created by Sterling on 7/25/2024 in #firmware-and-baremetal
How can I create and implement DDR memory in Verilog on an FPGA?
Moreover,for the processor applications, latency is usually more important than bandwidth especially when your caching strategy is simple.
Otherwise, you will need to look into predictive prefetching to hide your latency
7 replies
DIIDevHeads IoT Integration Server
•Created by Sterling on 7/25/2024 in #firmware-and-baremetal
How can I create and implement DDR memory in Verilog on an FPGA?
Hi @UC GEE, just plug and play slowly.
l tried both the DDR controllers from Altera and Xilinx,and their latency is humongous. Their bandwidth is actually fine but latency is horrible.
7 replies