How can I create and implement DDR memory in Verilog on an FPGA?
I want to create a DDR memory using Verilog and implement it on an FPGA. I wanted to ask for resources that could help me get started. I have no idea of how DDR RAM works, I browsed some sourcces and came across DFI protocol, DDR PHY IP, but I didn't understand much. I want a basic application note or white paper that can get me started on understanding the memories.
The main goal is to create a whole processor with all features possible below.
I have created a RISC processor with custom ISA, which is 16-bit. I want to increases its functionality.
I have implemented 2-bit branch predictor in it. To be done: Adding UART to my processor so that I can write to the Data memory directly instead of mentioning the instructions directly in the Verilog code of the data memory itself. (designed, yet to be tested) The next step that I think, should be to integrate a RAM to it. Add Cache and design whole memory sub-system. I also want to create a SPI Flash so that I can put my custom BIOS in it. Any suggestions to what could I do more on my processor? @Middleware & OS
I have implemented 2-bit branch predictor in it. To be done: Adding UART to my processor so that I can write to the Data memory directly instead of mentioning the instructions directly in the Verilog code of the data memory itself. (designed, yet to be tested) The next step that I think, should be to integrate a RAM to it. Add Cache and design whole memory sub-system. I also want to create a SPI Flash so that I can put my custom BIOS in it. Any suggestions to what could I do more on my processor? @Middleware & OS
2 Replies
Hi @UC GEE, just plug and play slowly.
l tried both the DDR controllers from Altera and Xilinx,and their latency is humongous. Their bandwidth is actually fine but latency is horrible.
Moreover,for the processor applications, latency is usually more important than bandwidth especially when your caching strategy is simple.
Otherwise, you will need to look into predictive prefetching to hide your latency
Ohh...Ok thanks 👍 @Sterling
But ,do u have any idea on how to evaluate the performance of the DDR controllers in terms of latency and bandwidth?
Well, you will have to measure the total bandwidth utilization of the DDR controller, find out if it could achieve around 76-83% of the theoretical maximum bandwidth.
If this isn't enough to meet your 512MB/s per port requirement, you can as well to use the on-chip memory in to the support to the DDR controller, it will help you to meet your bandwidth requirements, and you will observe that this could reduce latency compared to using just the DDR controller.
This is cool💯 .. Thanks for the vital tips @Sterling