Sterling
DIIDevHeads IoT Integration Server
•Created by UC GEE on 7/10/2024 in #middleware-and-os
Best tools for generating UML diagrams from SystemVerilog code for thesis writeup?
@UC GEE I would recommend you to make use of an automated parsing tool like Doxygen or SV-UVM-UML. These tools can parse your SystemVerilog code and generate UML diagrams automatically, which can save you a lot of time and effort.
8 replies