Best tools for generating UML diagrams from SystemVerilog code for thesis writeup?
I'm working on my thesis writeup and need to document a reasonably complex verification framework written in SystemVerilog. The framework consists of several classes with parameterized types and inheritance relationships.
I'd like to generate UML diagrams to effectively represent this structure, ideally in the simplest and most concise way possible. It's been a while since I last used UML diagramming tools, so I'd prefer to avoid manually creating them using tools like draw.io to minimize errors and time investment.
Solution:Jump to solution
Well, UML diagrams, whether automatically or manually generated, can be used to review the design of a SystemVerilog module or system. They can help you identify potential issues, such as complex dependencies or missing connections, early in the development process.
6 Replies
Here are my preferences:
1) Automated Parsing Tool: Ideally, I'd like a tool that parses the SystemVerilog code and automatically generates UML diagrams. This would be the most efficient approach. If the tool outputs a basic diagram, I can then edit it for clarity and presentation.
2) Simple Manual Input Tool: If an automated parsing tool isn't available, a simple tool that allows me to describe the class relationships manually would be helpful. This tool could accept input like:
Has anyone encountered similar
challenges?
What tools or approaches would you recommend for generating UML diagrams from SystemVerilog code, especially for a thesis with a focus on clarity and efficiency? @Middleware & OS
What tools or approaches would you recommend for generating UML diagrams from SystemVerilog code, especially for a thesis with a focus on clarity and efficiency? @Middleware & OS
@UC GEE I would recommend you to make use of an automated parsing tool like Doxygen or SV-UVM-UML. These tools can parse your SystemVerilog code and generate UML diagrams automatically, which can save you a lot of time and effort.
However , if you prefer a manual approach, Try out PlantUML or Mermaid, either of them would be a good choice. 🙂
But Please @Sterling ,what are some other potential use cases for automatically or manually generated UML diagrams beyond thesis writing, such as in SystemVerilog code development and review?🤔
Solution
Well, UML diagrams, whether automatically or manually generated, can be used to review the design of a SystemVerilog module or system. They can help you identify potential issues, such as complex dependencies or missing connections, early in the development process.
Ohh ...Ok Thanks @Sterling