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Created by UC GEE on 7/10/2024 in #middleware-and-os
Best tools for generating UML diagrams from SystemVerilog code for thesis writeup?
Here are my preferences: 1) Automated Parsing Tool: Ideally, I'd like a tool that parses the SystemVerilog code and automatically generates UML diagrams. This would be the most efficient approach. If the tool outputs a basic diagram, I can then edit it for clarity and presentation. 2) Simple Manual Input Tool: If an automated parsing tool isn't available, a simple tool that allows me to describe the class relationships manually would be helpful. This tool could accept input like: 
(Y is abstract, contains these methods, X extends Y and overrides these methods, ...)
(Y is abstract, contains these methods, X extends Y and overrides these methods, ...)
Has anyone encountered similar challenges?
What tools or approaches would you recommend for generating UML diagrams from SystemVerilog code, especially for a thesis with a focus on clarity and efficiency? @Middleware & OS
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