Marvee Amasi
Marvee Amasi
DIIDevHeads IoT Integration Server
Created by Marvee Amasi on 12/16/2024 in #🪲-firmware-and-baremetal
What Are the Architectural Constraints in Haswell That Limit CPE Optimization?
On the memory side, I am curious , do you think cache alignment or prefetching techniques could significantly impact the CPE, even with SIMD? Is there even a way to track how well my cache usage is optimized on the Haswell architecture, perhaps using perf or another tool?
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