hemalchevli
DIIDevHeads IoT Integration Server
•Created by Nayel on 8/2/2024 in #pcb-and-analog
How to optimize PCB design for DRV8320 and STM32G431RBT6TR to minimize vias?
hi
sorry for the late reply, I was on holiday.
First, I think the reset pin is missing a pullup resistor.
Before commenting on the vias, I want to know what's your layer stack up? I think at minimum you should use 4 layers.
You can check out the reference designs by TI, see how they are doing the layout for the DRV chip.
I'd add test points for all signals of interest, especially the gate drive signals.
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