Enthernet Code
DIIDevHeads IoT Integration Server
•Created by UC GEE on 7/19/2024 in #📦-middleware-and-os
Transitioning from Artix 7 to Zynq SoC for Image Processing and Storage
If you want your FPGA to write data to the RAM memory of the processor system, then your FPGA must implement the DMA engine.
It can be easily done with HLS (see https://docs.amd.com/r/en-US/ug1399-vitis-hls/AXI4-Master-Interface and https://github.com/Xilinx/Vitis-HLS-Introductory-Examples/blob/master/Interface/Memory/using\_axi\_master/example.cpp ). In HDL it is more complicated.
If you want to know more, you may read http://www.zynqbook.com/.
It can be easily done with HLS (see https://docs.amd.com/r/en-US/ug1399-vitis-hls/AXI4-Master-Interface and https://github.com/Xilinx/Vitis-HLS-Introductory-Examples/blob/master/Interface/Memory/using\_axi\_master/example.cpp ). In HDL it is more complicated.
If you want to know more, you may read http://www.zynqbook.com/.
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