barafael
DIIDevHeads IoT Integration Server
•Created by Marvee Amasi on 5/6/2024 in #middleware-and-os
Memory Operations During Context Switch: Impact on Priority Tasks?
In case you are interested in a fresh take on this domain, have a look at rtic.rs
Hardware-based RTOS-like scheduling for cortex-m and riscv clic, statically guaranteeing absence of priority inversion, deadlock, and data races. Locking is 1x RMW
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