Manuel
DIIDevHeads IoT Integration Server
•Created by Manuel on 4/25/2024 in #firmware-and-baremetal
Has anyone experience with the integrated pcie block from the xilinx 7 series fpga's?
@Navadeep acting as edge. Porting an existing project from virtex 5 to artix 7. Yes, added from IP repository, configured it. It shows up on the cpu, but as simple communication controller (class_code 0700) instead of the configured memory controller (class_code 0500). I checked all settings, grepped for 0700 in the sources, but have no Idea, why it identifies as such. Other settings are fine.
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