Navadeep
DIIDevHeads IoT Integration Server
•Created by Manuel on 4/25/2024 in #firmware-and-baremetal
Has anyone experience with the integrated pcie block from the xilinx 7 series fpga's?
I have explore this on Zynq Ultrascale+ where there is a specific mapping to the hard IP in the SoC and custom block is implementable as well on the FPGA fabric. In spartan 7 I suppose you're adding it from the IP repository of vivado block designer?
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