brotherjoons Comments - Answer Overflow

For ease of use and quick deployments, I am inclined to avail myself of paid tools such as Sourcedefender and Secupy. Minimal changes would be done to the existing code and there would be no noticeable effect or non at all on performance (as they advertise). For obfuscating the source codes using free tools, I am inclined to use Cython. Here the Python files are converted to C and compiled into machine code, which cannot easily be reversed and should be enough to thwart undetermined attempters. However, this would involve a cycle of testing/retesting to ensure that there are no regressions on functionality or bad effects on the performance. I would like to seek the community's inputs on the best practices how to approach this. Thanks.

8 replies

DIIDevHeads IoT Integration Server

•Created by techielew on 1/18/2024 in #general-dev-chat

Python source code protection from read

Thanks @techielew . As additional info on the context of the use case. The Python code runs on a RasPi to provide entertainment. The RasPi is integrated to another machine that is a wellness product. The purpose of the encryption is for IP protection (against copying or cloning)

8 replies

DIIDevHeads IoT Integration Server

•Created by brotherjoons on 1/14/2024 in #pcb-and-analog

Slow rise time on SD_CLK causes boot failure

Hi @abhishek awasthi @ShreeshaN @Navadeep @Priyanka Singh - thank you for sharing your insights. The reference design (SDHC schematic from the initial post, which is from LS1043A-RDB) also has the 10k R pull up on the SD_CLK line. There's currently logistics issue (I have the debugger tool but the actual failing board is halfway across the globe) and the board on my possession doesn't exhibit the behavior. We are currently ruling them as chip issue / isolated mfg issue but I will surely let everyone know how it goes.

12 replies

DIIDevHeads IoT Integration Server

•Created by brotherjoons on 1/14/2024 in #pcb-and-analog

Slow rise time on SD_CLK causes boot failure

Hello @Navadeep , the removal of R65(10K) has little effect on the rise time of the SD_CLK signal. We were considering the cases as chip failures. We are replacing the chips then retest. Thanks

12 replies

DIIDevHeads IoT Integration Server

•Created by brotherjoons on 1/14/2024 in #pcb-and-analog

Slow rise time on SD_CLK causes boot failure

Thank you for the insights @Navadeep

12 replies

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